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19-1619; Rev 0; 1/00
KIT ATION EVALU BLE AVAILA
2-Wire, 4-20mA Smart Signal Conditioner
General Description Features
o Highly Integrated Sensor Signal Conditioner for 2-Wire, 4-20mA Transmitters o Sensor Errors Trimmed Using Correction Coefficients Stored in Internal EEPROM-- Eliminates the Need for Laser Trimming and Potentiometers o Compensates Offset, Offset TC, FSO, FSOTC, FSO Linearity o Programmable Current Source (0.1mA to 2.0mA) for Sensor Excitation o Fast Signal-Path Settling Time (1ms) o Accepts Sensor Outputs from +1mV/V to +40mV/V o Fully Analog Signal Path o Internal or External Temperature Reference Compensation o Automated Pilot Production (Calibration/ Compensation) System Available o Write Protection for EEPROM Data Security
MAX1459
The MAX1459 highly integrated analog-sensor signal conditioner is optimized for piezoresistive sensor calibration and compensation with minimal external components. It includes a programmable current source for sensor excitation, a 3-bit programmable-gain amplifier (PGA), a 128-bit internal EEPROM, and four 12-bit DACs. Achieving a total error factor within 1% of the sensor's repeatability errors, the MAX1459 compensates offset, offset temperature coefficient (offset TC), full-span output (FSO), FSO temperature coefficient (FSOTC), and FSO nonlinearity of silicon piezoresistive sensors. The MAX1459 calibrates and compensates first-order temperature errors by adjusting the offset and span of the input signal through digital-to-analog converters (DACs), thereby eliminating quantization noise. The MAX1459 allows temperature compensation via the external sensor, an internal temperature-dependent resistor, or a dedicated external temperature transducer. Accuracies better than 0.5% can be achieved with low-cost external temperature sensors (i.e., silicon transistor), depending on sensor choice. Built-in testability features on the MAX1459 result in the integration of three traditional sensor-manufacturing operations into one automated process: * Pretest: Data acquisition of sensor performance under the control of a host test computer. * Calibration and compensation: Computation and storage (in an internal EEPROM) of calibration and compensation coefficients computed by the test computer and downloaded to the MAX1459. * Final test operation: Verification of transducer calibration and compensation without removal from the pretest socket. Although optimized for use with piezoresistive sensors, the MAX1459 may also be used with other resistive sensors (i.e., accelerometers and strain gauges) with some additional external components.
For custom versions of the MAX1459, see the Customization section at end of data sheet.
Ordering Information
PART MAX1459CAP MAX1459C/D TEMP. RANGE 0C to +70C 0C to +70C PIN-PACKAGE 20 SSOP Dice*
MAX1459AAP -40C to +125C 20 SSOP *Dice are tested at TA = +25C, DC parameters only. Functional Diagram appears at end of data sheet.
Pin Configuration
TOP VIEW
SCLK 1 CS 2 DIO 3 WE 4 FSOTC 5 AMP+ 6 AMP- 7 AMPOUT 8 TEMPIN 9 ISRC 10 20 VDD 19 NBIAS 18 CK50
MAX1459
17 TEMP2 16 TEMP1 15 INM 14 INP 13 BDRIVE 12 VSS 11 OUT
________________________Applications
4-20mA Transmitters Piezoresistive Pressure and Acceleration Industrial Pressure Sensors Load Cells/Wheatstone Bridges Strain Gauges Temperature Sensors
SSOP 1
________________________________________________________________ Maxim Integrated Products
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2-Wire, 4-20mA Smart Signal Conditioner MAX1459
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD to VSS......................................-0.3V to +6V All Other Pins ...................................(VSS - 0.3V) to (VDD + 0.3V) Short-Circuit Duration, FSOTC, OUT, BDRIVE ...........Continuous Continuous Power Dissipation (TA = +70C) 20-Pin SSOP (derate 8.00mW/C above +70C) ..........640mW Operating Temperature Ranges MAX1459CAP ......................................................0C to +70C MAX1459AAP .................................................-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VSS = 0, TA = +25C, unless otherwise noted.) PARAMETER GENERAL CHARACTERISTICS Supply Voltage Supply Current ANALOG INPUT (PGA) Input Impedance Input-Referred Offset Tempco Amplifier Gain Nonlinearity Output Step Response Common-Mode Rejection Ratio Input-Referred Adjustable Offset Range Input-Referred Adjustable FullSpan Output (FSO) Range ANALOG OUTPUT (PGA) Differential Signal Gain Range Minimum Differential Signal Gain Differential Signal Gain Tempco Output Voltage Swing Output Current Range Output Noise CURRENT SOURCE Bridge Current Range Bridge Voltage Swing Reference Input Voltage Range (ISRC) IBDRIVE VBDRIVE VISRC IBDRIVE = 2mA 0.1 VSS + 1.3 VSS + 1.3 0.5 2.0 VDD - 1.3 VDD - 1.3 mA V V Selectable in eight steps TA = TMIN to TMAX TA = TMIN to TMAX No load 10k load VOUT = (VSS + 0.25V) to (VDD - 0.25V) DC to 10Hz (gain = 41, source impedance = 5k) VSS + 0.05 VSS + 0.25 -0.45 (sink) 500 +36 +41 to +230 +41 50 VDD - 0.05 VDD - 0.25 0.45 (source) +44 V/V V/V ppm/C V mA VRMS CMRR 63% of final value From VSS to VDD At minimum gain (Note 4) (Note 5) RIN (Notes 2, 3) 1 0.5 0.01 2 90 150 +1 to +40 M V/C %VDD ms dB mV mV/V VDD IDD RNBIAS = 402k, VDD = 5.0V (Note 1) 4.5 5.0 2.0 5.5 2.5 V mA SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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2-Wire, 4-20mA Smart Signal Conditioner
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VSS = 0, TA = +25C, unless otherwise noted.) PARAMETER DAC Resolution Differential Nonlinearity Offset DAC Bit Weight Offset TC DAC Bit Weight FSO DAC Bit Weight FSOTC DAC Bit Weight IRO DAC DAC Resolution DAC Bit Weight FSOTC BUFFER (FSOTC Pin) Output Voltage Swing Current Drive INTERNAL RESISTORS Current Source Reference Resistor FSO Trim Resistor Temperature-Dependent Resistor AUXILIARY OP AMP Input Common-Mode Range Open-Loop Gain Offset Voltage (as unity-gain follower) Output Swing Output Current CMR AV VIN = VDD/2 No load -30 VSS + 0.05 1 VSS 60 30 VDD - 0.05 VDD V dB mV V mA RISRC RFTC RTEMP 100 100 100 k k k No load, VB = 5V VFSOTC = 2.5V 0.2 -20 4.0 20 V A Input referred, VDD = 5V (Note 6) 3 9 Bits mV/bit DNL VOUT Code VOUT Code VISRC Code VFSOT Code DAC reference = VDD = 5.0V DAC reference = VBDRIVE = 2.5V DAC reference = VDD = 5.0V DAC reference = VBDRIVE = 2.5V SYMBOL CONDITIONS MIN TYP 12 1.5 2.8 1.4 1.22 0.6 MAX UNITS Bits LSB mV/bit mV/bit mV/bit mV/bit DIGITAL-TO-ANALOG CONVERTERS
MAX1459
3
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2-Wire, 4-20mA Smart Signal Conditioner MAX1459
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VSS = 0, TA = +25C, unless otherwise noted.) PARAMETER DIGITAL PINS High-Level Input Voltage Low-Level Input Voltage Input Hysteresis High-Level Output Voltage Low-Level Output Voltage Note 1: Note 2: Note 3: Note 4: Note 5: VOH VOL ISOURCE = 1mA ISINK = 2mA 4 0.5 VIH VIL 2 0.75 x VDD 0.25 x VDD V V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
Excludes the sensor or load current. All electronics temperature errors are compensated together with sensor errors. The sensor and the MAX1459 must always be at the same temperature during calibration and use. This is the maximum allowable sensor offset. This is the sensor's sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge voltage of 2.5V. Sensors smaller than +10mV/V require an auxiliary op amp. Note 6: Bit weight is ratiometric to VDD.
__________________________________________Typical Operating Characteristics
(VDD = +5V, VSS = 0, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX1459 toc01
RTEMP vs. TEMPERATURE
MAX1459 toc02
VOUT vs. TEMPERATURE
4.5 4.0 3.5 VOUT (V) 3.0 2.5 2.0 1.5 1.0 0.5 VOUT = 2.47V AT +25C VIN = 0 VOUT = 2.5V AT +25C VIN = 56.5mV
MAX1459 toc03
2.5 VOUT = 2.47V AT +25C 2.0 SUPPLY CURRENT (mA)
200 180 160 140 RTEMP ()
5.0
1.5
120 100 80 60
1.0
0.5
40 20
0 -40
-20
0
20
40
60
80
100 120
0 -40
-20
0
20
40
60
80
100 120
0 -40
-20
0
20
40
60
80
100 120
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
4
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2-Wire, 4-20mA Smart Signal Conditioner
Pin Description
PIN 1 2 3 NAME SCLK CS DIO FUNCTION Data Clock Input. Used only during programming/testing. Internally pulled to VSS with a 1M (typical) resistor. Data is clocked in on the rising edge of the clock. Recommended SCLK frequency is below 50kHz. Chip-Select Input. The MAX1459 is selected when this pin is high. When low, OUT and DIO become high impedance. Internally pulled to VDD with a 1M (typical) resistor. Leave unconnected for normal operation. Data Input/Output. Used only during programming/testing. Internally pulled to VSS with a 1M (typical) resistor. High impedance when CS is low. Write Enable, Dual-Function Input Pin. Used to enable EEPROM erase/write operations. Also used to set the DAC refresh-rate mode. Internally pulled to VDD with a 1M (typ) resistor. See the Chip-Select (CS) and Write-Enable (WE) section. Buffered Full-Span Output Temperature Coefficient DAC Output. An internal 100k resistor (RFTC) connects FSOTC to ISRC (see Functional Diagram). Optionally, external resistors can be used in place of or in parallel with RFTC and RISC. Auxiliary Op Amp Positive Input Auxiliary Op Amp Negative Input Auxiliary Op Amp Output Input pin for an External Temperature-Dependent Reference Voltage for FSOTC DAC and OTC DAC. In the default mode, the MAX1459 uses the temperature-dependent bridge drive voltage as the FSOTC DAC and OTC DAC reference. Current Source Reference. An internal 100k resistor (RISRC) connects ISRC to VSS (see Functional Diagram). Optionally, external resistors can be used in place of or in parallel with RFTC and RISRC. Output Voltage. OUT is a Rail-to-Rail(R) output that can drive resistive loads down to 10k and capacitive loads up to 0.1F. Negative Power Supply Sensor Excitation Current Output. The current source that drives the bridge. Positive Sensor Input. Input impedance is typically 1M. Rail-to-rail input range. Negative Sensor Input. Input impedance is typically 1M. Rail-to-rail input range. Temperature Sensor Terminal 1 Temperature Sensor Terminal 2. RTEMP is a 100k temperature-dependent resistor with 4600ppm/C tempco. Clock Output, nominally 50kHz Chip Current Bias Source. Connect an external 402k 1% resistor between VDD and NBIAS. Positive Power-Supply Input. Connect a 0.1F capacitor from VDD to VSS.
MAX1459
4
WE
5 6 7 8 9
FSOTC AMP+ AMPAMPOUT TEMPIN
10 11 12 13 14 15 16 17 18 19 20
ISRC OUT VSS BDRIVE INP INM TEMP1 TEMP2 CK50 NBIAS VDD
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. _______________________________________________________________________________________ 5
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
_______________Detailed Description
The MAX1459 provides an analog amplification path for the sensor signal and a digital path for calibration and temperature correction. Calibration and correction is achieved by varying the offset and gain of a programmable-gain amplifier (PGA) and by varying the sensor bridge current. The PGA utilizes a switched-capacitor CMOS technology, with an input-referred offset trimming range of 63mV (9mV steps). An additional output-referred fine offset trim is provided by the offset DAC (approximately 2.8mV steps). The PGA provides eight gain values from +41V/V to +230V/V. The bridge current source is programmable from 0.1mA to 2mA. The MAX1459 uses four 12-bit DACs with calibration coefficients stored by the user in an internal 128-bit EEPROM. This memory contains the following information as 12-bit-wide words: * Configuration register * Offset calibration coefficient * Offset temperature error compensation coefficient * Full-span output (FSO) calibration coefficient * FSO temperature error compensation coefficient * 24 user-defined bits for customer programming of manufacturing data (e.g., serial number and date) Figure 1 shows a typical pressure-sensor output and defines the offset, full-scale, and FSO values as a function of voltage.
4.5
VOLTAGE (V)
FULL-SPAN OUTPUT (FSO)
FULL-SCALE (FS) 0.5 OFFSET PMIN PMAX PRESSURE
Figure 1. Typical Pressure-Sensor Output
DAC alters the tempco of the current source. When the tempco of the bridge voltage is equal in magnitude and opposite in polarity to the TCS, the FSOTC errors are compensated and FSO will be constant with temperature.
OFFSET TC Compensation
Compensating offset TC errors involves first measuring the uncompensated offset TC error, then determining what percentage of the temperature-dependent voltage VBDRIVE must be added to the output summing junction to correct the error. Use the offset TC DAC to adjust the amount of BDRIVE voltage that is added to the output summing junction (Figure 3).
FSOTC Compensation
Silicon piezoresistive transducers (PRTs) exhibit a large positive input resistance tempco (TCR) so that, while under constant current excitation, the bridge voltage (V BDRIVE ) increases with temperature. This dependence of VBDRIVE on the sensor temperature can be used to compensate the sensor temperature errors. PRTs also have a large negative full-span output sensitivity tempco (TCS) so that, with constant voltage excitation, FSO will decrease with temperature, causing a full-span output temperature coefficient (FSOTC) error. However, if the bridge voltage can be made to increase with temperature at the same rate that TCS decreases with temperature, the FSO will remain constant. FSOTC compensation is accomplished by resistor RFTC and the FSOTC DAC, which modulate the excitation reference current at ISRC as a function of temperature (Figure 2). FSO DAC sets V ISRC and remains constant with temperature while the voltage at FSOTC varies with temperature. FSOTC is the buffered output of the FSOTC DAC. The reference DAC voltage is VBDRIVE, which is temperature dependent. The FSOTC
6
Analog Signal Path
The fully differential analog signal path consists of four stages: * Front-end summing junction for coarse offset correction * 3-bit PGA with eight selectable gains ranging from 41 through 230 * Three-input-channel summing junction * Differential to single-ended output buffer with rail-torail output (Figure 3) Coarse Offset Correction The sensor output is first fed into a differential summing junction (INM (negative input) and INP (positive input)) with a CMRR > 90dB, an input impedance of approximately 1M, and a common-mode input voltage range from VSS to VDD. At this summing junction, a coarse offset-correction voltage is added, and the resultant volt-
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2-Wire, 4-20mA Smart Signal Conditioner MAX1459
VDD FSO DAC VDD
I = IISRC ISRC
AA 12IISRC = IBDRIVE BDRIVE
FSOTC DAC
FSOTC
RFTC
RISRC
EXTERNAL SENSOR
Figure 2. Bridge Excitation Circuit
1.25% VDD IRO DAC
BDRIVE OFFTC DAC A2 A1 A0 SOTC
DAC bits (C2, C1, C0, and IRO sign bit) are programmed in the configuration register (see Internal EEPROM section). Programmable-Gain Amplifier The programmable-gain amplifier (PGA), which is used to set the coarse FSO, uses a switched-capacitor CMOS technology and contains eight selectable gain levels from 41 to 230, in increments of 27 (Table 2). The output of the PGA is fed to the output summing junction. The three PGA gain bits A2, A1, and A0 are stored in the configuration register. Output Summing Junction The third stage in the analog signal path consists of a summing junction for the PGA output, offset correction, and the offset TC correction. Both the offset and the offset TC correction voltages are gained by a factor of 2.3 before being fed into the summing junction, increasing the offset and offset TC correction range. The offset sign bit and offset TC sign bit are stored in the configuration register. The offset sign bit determines whether the offset correction voltage is added to (sign bit is high) or subtracted from (sign bit is low) the PGA output. Negative offset TC errors require a logic high for the offset TC sign bit. Alternately, positive offset TC errors dictate a logic low for the offset TC sign bit. The output of the summing junction is fed to the output buffer.
A = 2.3
INP INM
PGA
A = 2.3
A=1
OUT
VDD OFFSET DAC SOFF
Figure 3. Signal-Path Block Diagram
age is fed into the PGA. The 3-bit (plus sign) inputreferred offset DAC (IRO DAC) generates the coarse offset-correction voltage. The DAC voltage reference is 1.25% of VDD; thus, a VDD of 5V results in a front-end offset-correction voltage ranging from -63mV to +63mV, in 9mV steps (Table 1). To add an offset to the input signal, set the IRO sign bit high; to subtract an offset from the input signal, set the IRO sign bit low. The IRO
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2-Wire, 4-20mA Smart Signal Conditioner MAX1459
Table 1. Input-Referred Offset DAC Correction Values
IRO DAC OFFSET CORRECTION PERCENT OF VDD (%) +1.25 +1.08 +0.90 +0.72 +0.54 +0.36 +0.18 0 -0.18 -0.36 -0.54 -0.72 -0.90 -1.08 -1.25 OFFSET CORRECTION AT VDD = 5V (mV) +63 +54 +45 +36 +27 +18 +9 0 -9 -18 -27 -36 -45 -54 -63
be shorted to either VDD or VSS indefinitely. If CS is brought low, OUT goes high impedance, resulting in typical output impedance of 1M. This feature allows parallel MAX1459 connections, reducing test system wire harness complexity.
Bridge Drive
Fine FSO correction is accomplished by varying the sensor excitation current with the 12-bit FSO DAC (Figure 2). Sensor bridge excitation is performed by a programmable current source capable of delivering up to 2mA. The reference current at ISRC is established by resistor RISRC and by the voltage at node ISRC (controlled by the FSO DAC). The reference current flowing through this pin is multiplied by a current mirror (AA 12) and then made available at BDRIVE for sensor excitation. Modulation of this current with respect to temperature can be used to correct FSOTC errors, while modulation with respect to the output voltage (VOUT) can be used to correct FSO linearity errors.
VALUE +7 +6 +5 +4 +3 +2 +1 -0 -1 -2 -3 -4 -5 -6 -7
SIGN 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
C2 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1
C1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1
C0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Voltage Drive Sensor
For sensors with negligible FSOTC, the MAX1459 can be configured as a fixed-voltage drive by shorting ISRC and BDRIVE. Offset TC can then be compensated with RTEMP. Set configuration register bit 5 to 1, and connect TEMPIN to a temperature-dependent voltage source. This source can easily be generated by inducing a current through RTEMP. For more information on this application, refer to the MAX1459 Reference Manual.
Table 2. PGA Gain Settings and IRO DAC Step Size
PGA VALUE 0 1 2 3 4 5 6 7 A2 A1 A0 PGA GAIN (+V/+V) 41 68 95 122 149 176 203 230 OUTPUTREFERRED IRO DAC STEP SIZE (VDD = 5V) (V) 0.369 0.612 0.855 1.098 1.341 1.584 1.827 2.070
Digital-to-Analog Converters
The four 12-bit, sigma-delta DACs typically settle in less than 100ms. The four DACs have a corresponding memory register in EEPROM for storage of correction coefficients. The FSO DAC takes its reference from VDD and controls VISRC, which sets the baseline sensor excitation current. The FSO DAC is used for fine adjustments to the FSO. The offset DAC also takes its reference from VDD and provides a 1.22mV resolution with a VDD of 5V. The output of the offset DAC is fed into the output summing junction where it is gained by approximately 2.3, which increases the resulting output-referred offset-correction resolution to 2.8mV. Both the offset TC and FSOTC DACs take their references from a temperature-dependent voltage. In default mode, this voltage is internally connected to BDRIVE. Alternatively, a different temperature sensor can be used through TEMPIN by setting bit 5 of the configuration register. This temperature sensor can be either RTEMP or an external temperature resistor.
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Output Buffer
The output buffer (OUT) can swing within 50mV of the supply rails with no load, or within 0.25V of either rail while driving a 10k load. OUT can easily drive 0.1F of capacitance. The output is current limited and can
8
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2-Wire, 4-20mA Smart Signal Conditioner
The offset TC DAC output is fed into the output summing junction where it is gained by approximately 2.3, thereby increasing the offset TC correction range. The buffered FSOTC DAC output is available at FSOTC and is connected to ISRC via RFTC to correct FSOTC errors.
Internal EEPROM
The MAX1459 has a 128-bit internal EEPROM arranged as eight 16-bit registers. The 4 uppermost bits for each register are reserved. The internal EEPROM is used to store the following (also shown in the memory map in Table 4): * Configuration register (Table 3) * 12-bit calibration coefficients for the offset and FSO DACs * 12-bit compensation coefficients for the offset TC and FSOTC DACs * Two general-purpose registers available to the user for storing process information such as serial number, batch date, and check sums The EEPROM is bit addressable. Program the EEPROM using the following steps, where the bits have addresses from 0 to 127 (07F hex): 1) Read the entire EEPROM, and temporarily store the reserved bits. 2) Erase the entire EEPROM, which causes all bits to be 0 (see the ERASE EEPROM Command section). 3) Program 1 to the required bits, including the reserved bits (see the WRITE EEPROM BIT Command section). 4) Read the whole EEPROM, either with the READ EEPROM BIT or with the READ EEPROM MATRIX commands (see the READ EEPROM BIT Command and READ EEPROM MATRIX Command sections). Configuration Register The configuration register (Table 3) determines the PGA gain, the polarity of the offset and offset TC coefficients, and the coarse offset correction (IRO DAC). It also enables/disables internal resistors (R FTC and RISRC). DAC Registers The offset, offset TC, FSO, and FSOTC registers store the coefficients used by their respective calibration/ compensation DACs.
MAX1459
Internal Resistors
The MAX1459 contains three internal resistors (RISRC, RFTC, and RTEMP) optimized for common silicon PRTs. RISRC (in conjunction with the FSO DAC) programs the nominal sensor excitation current. RFTC (in conjunction with the FSOTC DAC) compensates the FSOTC errors. Both RISRC and RFTC have a nominal value of 100k. If external resistors are used, RISRC and RFTC can be disabled by setting the appropriate bit (address 07h reset to zero) in the configuration register (Table 3). R TEMP is a high-tempco resistor with a TC of +4600ppm/C and a nominal resistance of 100k at +25C. This resistor can be used with certain sensor types that require an external temperature sensor. The two RTEMP terminals are available as pin 16 and pin 17 of the MAX1459.
Table 3. Configuration Register Description
CONFIGURATION REGISTER BIT EEPROM ADDRESS (hex) 0B 0A 09 08 07 06 05 04 03 02 01 00 DESCRIPTION IRO Sign, SIRO IRO MSB, C2 IRO, C1 IRO LSB, C0 RISRC/RFTC Selection Bit (0 = enable internal), IRS Reserved "0" Temperature Sensor Selection Bit (0 = default VBDRIVE) PGA Gain (MSB), A2 PGA Gain, A1 PGA Gain (LSB), A0 Offset Sign Bit, SOFF Offset TC Sign Bit, SOTC
11 10 9 8 7 6 5 4 3 2 1 0
Detailed Description of the Digital Lines
Chip-Select (CS) and Write-Enable (WE) CS is used to enable OUT, control serial communication, and force an update of the configuration and DAC registers: * A low on CS disables serial communication and places OUT in a high-impedance state. * A transition from low to high on CS forces an update of the configuration and DAC registers from the
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2-Wire, 4-20mA Smart Signal Conditioner MAX1459
Table 4. EEPROM Memory Map
EE Address Contents EE Address Contents EE Address Contents EE Address Contents EE Address Contents
0F 1 1F 1 2F 1 3F 1 0E 0 1E 0 2E 0 3E 0 0D 0 1D 0 2D 1 3D 1 0C 0 1C 1 2C 0 3C 1 1B MSB 2B MSB 3B MSB 3A 39 38 37 2A 29 28 27 1A 19 18 17 0B 0A 09 08 07 06 05 04 03 02 01 00 Configuration 16 15 14 13 12 11 10 LSB 24 23 22 21 20 LSB 34 33 32 31 30 LSB
Offset 26 25
Offset TC 36 35
FSO
4F 1
4E 1
4D 0
4C 0
4B MSB
4A
49
48
47
46
45
44
43
42
41
40 LSB
FSOTC
5F
5E 0
5D 0
5C 0
5B
5A
59
58
57
56
55
54
53
52
51
50
Reserved
0
Reserved
EE Address Contents EE Address Contents
6F 0
6E 0
6D 0
6C 0
6B
6A
69
68
67
66
65
64
63
62
61
60
User-Defined Bits
7F 0
7E 0
7D 0
7C 0
7B
7A
79
78
77
76
75
74
73
72
71
70
User-Defined Bits
= Reserved Bits Note: The MAX1459 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration and DAC registers will not be updated correctly.
EEPROM when the U bit of the INIT sequence is zero. * A transition from high to low on CS terminates programming mode. * A logic high on CS enables OUT and serial communication (see Communication Protocol section). WE controls the refresh rate for the internal configuration and DAC registers from the EEPROM and enables the erase/write operations. If communication has been initiated (see Communication Protocol section), internal register refresh is disabled. * A low on WE disables the erase/write operations and also disables register refreshing from the EEPROM.
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* A high on WE selects a refresh rate of approximately 400 times per second and enables EEPROM erase/write operations. * It is recommended that WE be connected to V SS after the MAX1459 EEPROM has been programmed. SCLK (Serial Clock) SCLK must be driven externally and is used to input commands to the MAX1459 or program the internal EEPROM contents. Input data on DIO is latched on the rising edge of SCLK.
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2-Wire, 4-20mA Smart Signal Conditioner
Data Input/Output The DIO line is an input/output pin used to issue commands to the MAX1459 (input mode) or read the EEPROM contents (output mode). In input mode (the default mode), data on DIO is latched on each rising edge of SCLK. Therefore, data on DIO must be stable at the rising edge of SCLK and should transition on the falling edge of SCLK. DIO will switch to output mode after receiving either the READ EEPROM command or the READ EEPROM MATRIX command. See the Read EEPROM section for detailed information. ter will be updated from the EEPROM on the next rising edge of CS (this is also the default on power-up). If the U bit is high (INIT SEQUENCE = AA hex), the DACs and configuration register will not be updated from the internal EEPROM; they will retain their current value on any subsequent CS rising edge. The MAX1459 continues to accept control words until CS is brought low.
MAX1459
Control Words
After receiving the INIT SEQUENCE on DIO, the MAX1459 begins latching in 16-bit control words, MSB first (Figure 5). The first 4 bits of the control word (the MSBs, CM3-CM0) are the command field. The last 12 bits (D11-D0) represent the data field. The MAX1459 supports the commands listed in Table 5.
Communication Protocol
To initiate communication, the first 8 bits on DIO after CS transitions from low to high must be 101010U0 (AA hex or A8 hex, defined as the INIT sequence). The MAX1459 will then begin accepting 16-bit control words (Figure 4). If the INIT SEQUENCE is not detected, all subsequent data on DIO is ignored until CS again transitions from low to high and the correct INIT SEQUENCE is received. The U bit of the INIT SEQUENCE controls the updating of the DACs and configuration register from the internal EEPROM. If this bit is low (U = 0, INIT SEQUENCE = A8 hex), all four internal DACs and the configuration regis-
No-OP Command (0 hex)
The no-operation (No-OP) command must be issued before and after the commands ERASE EEPROM and WRITE EEPROM BIT. In the case of the ERASE EEPROM command, the control word must be 0000 hex. In the case of the WRITE EEPROM BIT command, the command field must be 0h, and the data field must have, in its lower bits, the EEPROM address to be written (Figure 6). For example, to write location 1C hex of
CS tMIN = 1.5ms SCLK 8 CLK CYCLES 16 CLK CYCLES 16 CLK CYCLES n x 16 CLK CYCLES
DIO
X
1
0
1
0
1
0
U
0
CM3 CM2 DO CM3 CM2 DO CONTROL WORD CONTROL WORD CONTROL WORDS
INIT SEQUENCE
Figure 4. Communication Sequence
SCLK COMMAND MSB DIO LSB MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 CM3 CM2 CM1 CM0 D11 D10 DATA LSB D0
16-BIT CONTROL WORD MSB LSB
Figure 5. Control-Word Timing Diagram ______________________________________________________________________________________ 11
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
Table 5. MAX1459 Commands
FUNCTION No-OP ERASE EEPROM WRITE EEPROM BIT READ EEPROM BIT MAXIM RESERVED MAXIM RESERVED MAXIM RESERVED MAXIM RESERVED WRITE Data to Configuration Register WRITE Data to Offset DAC WRITE Data to Offset-TC DAC WRITE Data to FSO DAC WRITE Data to FSOTC DAC CONTROL OUTPUT MUX READ EEPROM MATRIX LOAD REGISTER HEX CM3 CM2 CM1 CM0 CODE 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
the EEPROM (one of the reserved bits), the necessary commands are: * 001C hex: No-OP command, with address 1C hex in the data field * 201C hex: WRITE EEPROM BIT command, with address 1C hex in the data field * 001C hex: No-OP command, with address 1C hex in the data field
ERASE EEPROM Command (1 hex)
When an ERASE EEPROM command is issued, all of the memory locations in the EEPROM are reset to a logic 0. The data field of the 16-bit word is ignored (Figure 7). Important: An internal charge pump develops voltages greater than 20V for EEPROM programming operations. The EEPROM control logic requires 10ms to erase the EEPROM. After sending a write or erase command, failure to wait 10ms before issuing another command may result in unreliable EEPROM operation. The maximum number of EEPROM ERASE cycles should not exceed 100.
WRITE EEPROM BIT Command (2 hex)
The WRITE EEPROM BIT command stores a logic high at the memory location specified by the lower 7 bits of the data field (D6-D0). The higher bits of the data field (D11-D7) are ignored (Figure 8). Note that to write to the internal EEPROM, WE and CS must be high. In
SCLK COMMAND MSB DIO 0 0 0 LSB MSB 0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 DATA LSB A0
16-BIT CONTROL WORD - NO-OP COMMAND (OOXX HEX) MSB LSB
Figure 6. No-OP Command Timing Diagram
SCLK COMMAND MSB DIO 0 0 0 LSB MSB 1 X X X X X X X X X X X DATA LSB X
16-BIT CONTROL WORD - ERASE EEPROM COMMAND (1XXX HEX) MSB LSB
Figure 7. ERASE EEPROM Command Timing Diagram 12 ______________________________________________________________________________________
2-Wire, 4-20mA Smart Signal Conditioner
addition, the EEPROM should only be written to at TA = +25C and VDD = +5V. Writing to the internal EEPROM is a time-consuming process and should only be done once. All calibration/compensation coefficients are determined by writing directly to the configuration and DAC registers. Use the following procedure to write these calibration/compensation coefficients to the EEPROM: 1) Initiate the No-OP command (0000 hex). 2) Initiate the ERASE EEPROM command (1000 hex). 3) Wait 10ms. 4) Initiate the No-OP command (0000 hex). 5) Initiate the No-OP command, with address of bit in the data field (00XX hex), where XX is the bit address in the data field. 6) Initiate the WRITE EEPROM BIT command, with the same bit address in the data field (20XX hex). 7) Wait 10ms. 8) Initiate the No-OP command, with the same bit address in the data field (00XX hex). 9) Return to step 5 until all necessary bits have been set. 10) Read EEPROM to verify that the correct calibration/ compensation coefficients have been stored.
READ EEPROM BIT Command (3 hex)
The READ EEPROM BIT command returns the bit stored at the memory location addressed by the lower 7 bits of the data field (D6-D0). The higher bits of the data field are ignored. Note that after a read command has been issued, the DIO lines become an output and the contents of the addressed EEPROM location will be available on DIO for the next 15 cycles of SCLK. On the falling edge of the 16th SCLK cycle after issuing the READ EEPROM command, DIO returns to input mode (Figure 9). DIO is stable on the rising edge of SCLK.
MAX1459
Writing to the Configuration, DAC, and Output Select Registers (Commands 8, 9, A, B, C, and D hex)
Commands 8 hex, 9 hex, A hex, B hex, and C hex write the 12 bits of the data field (D11-D0) directly to the configuration and DAC registers. These commands must be followed by the LOAD REGISTER command (Fxxx hex). Note that all four DACs and the configuration register can be updated without toggling the CS line after a valid INIT SEQUENCE (Figure 10).
OUTPUT SELECT Command (D hex)
The OUTPUT SELECT command switches the output pin to other internal nodes instead of the default PGA output (Figure 10). Table 6 lists the output mux settings.
SCLK COMMAND MSB DIO 0 0 1 LSB MSB 0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 DATA LSB A0
16-BIT CONTROL WORD - WRITE EEPROM BIT COMMAND (20XX HEX) MSB LSB
Figure 8. WRITE EEPROM BIT Command Timing Diagram
16 CLOCK CYCLES SCLK COMMAND MSB DIO 0 0 1 LSB MSB 1 0 0 0 0 0 D6 D5 D4 D3 D2 D1 DATA LSB D0
15 CLOCK CYCLES
16 CLOCK CYCLES
DIO IS AN OUTPUT PIN EE BIT DATA X CM3 CM2 D0 CONTROL WORD
16-BIT CONTROL WORD - READ EEPROM BIT COMMAND (30XX HEX) MSB LSB
Figure 9. Timing Diagram for READ EEPROM BIT ______________________________________________________________________________________ 13
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
Table 6. Output Mux Selection
MUX VALUE 0 (default power-up) 1 2 3 D1 0 0 1 1 D0 0 1 0 1 OUTPUT Conditioned Output Voltage (PGA) Sensor Bridge Voltage (VB) Current-Source Voltage (VSPAN) Power Supply Voltage (VDD)
__________Applications Information
Power-Up
At power-up, the following occurs: 1) The DAC and configuration registers are reset to zero. 2) CS transitions from low to high after power-up (an internal pull-up resistor ensures that this happens if CS is left unconnected), and the EEPROM contents are read and processed. 3) The DAC and configuration registers are updated either once (if WE is logic 0) or approximately 400 times per second (if WE is logic 1). 4) The MAX1459 begins accepting commands in a serial format on DIO immediately after receiving the INIT SEQUENCE command. The MAX1459 must be programmed for proper operation.
The output mux facilitates the test system to monitor different voltages through the output pin.
READ EEPROM MATRIX Command (E hex)
The contents of the entire 128-bit EEPROM is available on DIO upon issuing this command. Once the MAX1459 receives the READ EEPROM MATRIX command, DIO turns into an output for the next 128 clock cycles. After the 128th clock cycle, DIO returns to its default input mode and the MAX1459 is ready to accept new commands (Figure 11). Data on DIO changes on falling edges of SCLK and is stable on rising edges of SCLK. The EEPROM data on DIO is eight 16-bit words, MSB to LSB. The sequence is then 0F hex, 0E hex, 0D hex, ..., 00 hex (word 0), 1F hex, 1E hex, 1D hex, ... (word 1), ..., 7F hex, 7E hex, ..., 70 hex (word 7).
Compensation Procedure
The following compensation procedure was used to obtain the results shown in Table 7 and Figure 12. It assumes a pressure transducer with a +5V supply and an output voltage that is ratiometric to the supply voltage. The desired offset voltage (VOUT at PMIN) is 0.5V, and the desired FSO voltage (VOUT(PMAX) - VOUT(PMIN)) is 4V; thus, the FSO voltage (VOUT at PMAX) will be 4.5V (Figure 1). The procedure requires a minimum of two
SCLK COMMAND MSB DIO LSB MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 CM3 CM2 CM1 CM0 D11 D10 DATA LSB D0 1 1 1 1 X X X X X X X X X X X X COMMAND DATA
8 HEX, 9 HEX, A HEX, B HEX, C HEX, OR D HEX WRITE REGISTER COMMAND MSB LSB MSB
16 BIT CONTROL WORD - LOAD REGISTER COMMAND (FXXX HEX) LSB
Figure 10. Timing Diagram for Write Register Operations
16 CLOCK CYCLES SCLK COMMAND MSB DIO 1 1 1 LSB MSB 0 X X X X X X X X X X X DATA LSB X 0F 0E 00
16 CLOCK CYCLES
16 CLOCK CYCLES
16 CLOCK CYCLES
16 CLOCK CYCLES
DIO IS AN OUTPUT PIN FOR 128 CLOCK CYCLES 1F 1E 10 2F 2E 20 7F 7E 70 CM3 CM2 D0 CONTROL WORD
16-BIT CONTROL WORD - READ EEPROM MATRIX COMMAND (EXXX) MSB
WORD 0 WORD 1 WORD 2 LSB MSB LSB MSB LSB MSB LSB
WORD 7 MSB LSB
Figure 11. Timing Diagram for Reading the Entire EEPROM Content 14 ______________________________________________________________________________________
2-Wire, 4-20mA Smart Signal Conditioner
test pressures (e.g., zero and full scale) at two arbitrary test temperatures, T1 and T2. Ideally, T1 and T2 are the two points where we wish to perform best linear fit compensation. The following outlines a typical compensation procedure: 1) Perform coefficient initialization. 2) Perform FSO calibration. 3) Perform FSOTC compensation. 4) Perform offset TC compensation. 5) Perform offset calibration. ues depend on sensor behavior and require some sensor characterization data, which may be available from the sensor manufacturer. If not, the data can be generated by performing a two-temperature, two-pressure sensor evaluation. The required sensor information is shown in Table 8 and can be used to obtain the values for the parameters listed in Table 9. Selecting RISRC When using an external resistor, use the equation below to determine the value of RISRC, and place the resistor between ISRC and VSS. Since the 12-bit FSO DAC provides considerable dynamic range, the RISRC value need not be exact. Generally, any resistor value within 50% of the calculated value is acceptable. If both the internal resistors RISRC and RFTC are used, set the IRS bit at EEPROM address bit 07 hex low.
MAX1459
Coefficient Initialization
Select the resistor values and the PGA gain to prevent overload of the PGA and bridge current source. Determine whether the MAX1459's internal resistors are suitable or external resistors are necessary. These val-
Table 7. MAX1459 Calibration and Compensation
TYPICAL UNCOMPENSATED INPUT (SENSOR) NAME Offset FSO Offset TC Offset TC Nonlinearity FSO TC FSO TC Nonlinearity Temperature Range DESCRIPTION 80% FSO +15mV/V -17% FSO 0.7% FSO -35% FSO 0.5% FSO -40C to +125C FSO Accuracy Over Temp Range 20mV (0.5% FSO) VOUT Offset at +25C FSO at +25C Offset Accuracy Over Temp Range TYPICAL COMPENSATED TRANSDUCER OUTPUT NAME DESCRIPTION Ratiometric to VDD at 5.0V 0.500V 5mV 4.000V 5mV 28mV (0.7% FSO)
UNCOMPENSATED SENSOR ERROR
30 0.8 0.6 20 ERROR (% SPAN) ERROR (% FSO) 0.4
COMPENSATION TRANSDUCER ERROR
FSO 0.2 0 -0.2 -0.4 OFFSET
10
FSO OFFSET
0
-10 -0.6 -20 -50 0 50 TEMPERATURE (C) 100 150 -0.8 -50
0
50 TEMPERATURE (C)
100
150
Figure 12. Comparison of an Uncalibrated Sensor and a Temperature-Compensated Transducer ______________________________________________________________________________________ 15
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
Otherwise, set IRS high and connect external resistors as shown in Figure 13: RISRC 12 x Rb(T) 12 x 5k 60k where Rb(T) is the sensor input impedance at temperature T1 (+25C in this example). Selecting RFTC When using an external resistor, use the equation below to determine the value for RFTC, and place the resistor between ISRC and FSOTC. Since the 12-bit FSOTC DAC provides considerable dynamic range, the RFTC value need not be exact. Generally, any resistor value within 50% of the calculated value is acceptable: RFTC RISRC x 500ppm/C TCR - | TCS | 60k x 500ppm/C 60k 2600ppm/ C - | -2100ppm/ C |
Table 8. Sensor Information for Typical PRT
PARAMETER Rb(T) TCR S(T) TCS O(T) OTC SENSOR DESCRIPTION Bridge Impedance Bridge Impedance Tempco Sensitivity Sensitivity Tempco Offset Offset Tempco Sensitivity Linearity Error as % FSO, BSLF (best straight-line fit) Minimum Input Pressure Maximum Input Pressure TYPICAL VALUES 5k at +25C 2600ppm/C +1.5mV/V per PSI at +25C -2100ppm/C +12mV/V at +25C -1000ppm/C of FSO 0.1% FSO, BSLF 0 psi 10 psi
This approximation works best for bulk, micromachined, silicon PRTs. Negative values for RFTC indicate unconventional sensor behavior that can be compensated by the MAX1459 with additional external circuitry. Selecting the PGA Gain Setting To select the PGA gain setting, first calculate SensorFSO, the sensor full-span output voltage at T1: SensorFSO = S x VBDRIVE x P = +1.5mV/V per PSI x 2.5V x 10 PSI = 0.0375V where S is the sensor sensitivity at T1, VBDRIVE is the sensor excitation voltage (initially 2.5V), and P is the maximum pressure differential. Then calculate the ideal gain using the following formula, and select the nearest gain setting from Table 2: APGA OUTFSO SensorFSO 4V = +106V/V 0.0375V
S(p) PMIN PMAX
Table 9. Compensation Components and Values
PARAMETER RISRC DESCRIPTION Internal (approximately 100k) or usersupplied resistor that programs the nominal sensor excitation current Internal (approximately 100k) or usersupplied resistor that compensates FSOTC errors Programmable-gain amplifier gain Input-referred offset correction DAC value Input-referred offset sign bit Internal resistor selection bit Offset correction DAC coefficient Offset sign bit Offset TC compensation DAC coefficient Offset TC sign bit FSO trim DAC FSOTC compensation DAC
RFTC APGA IRO IRO Sign IRS OFF COEF OFF Sign OFFTC COEF OFFTC Sign FSO COEF FSOTC COEF 16
where OUTFSO is the desired calibrated transducer full-span output voltage, and SensorFSO is the sensor full-span output voltage at T1. In this example, a PGA value of 2 (gain of +95V/V) is the best selection. Determining Input-Referred OFFSET The input-referred offset (IRO) register is used to null any front-end sensor offset errors prior to amplification by the PGA. This reduces the possibility of saturating the PGA and maximizes the useful dynamic range of the PGA (particularly at the higher gain values).
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2-Wire, 4-20mA Smart Signal Conditioner MAX1459
+5V
VDD BDRIVE C2 0.1F COARSE OFFSET (IRO DAC)
MAX1459
RNBIAS = 402k 1% NBIAS
C1 0.1F
INP INM
PGA SELECT OUTPUT
OUT
SENSOR ISRC VDD AMPAMP+ AMPOUT FSOTC CONFIGURATION REGISTER 12-BIT D/A - OFFSET 12-BIT D/A - OFFSET TC 12-BIT D/A - FSO 12-BIT D/A - FSOTC A=1 RTEMP TEMP1 TEMP2
RISRC
RFTC RISRC VSS
RFTC
128-BIT EEPROM
CS WE SCLK DIO
DIGITAL INTERFACE
TEMPIN
VSS
Figure 13. Basic Ratiometric Output Configuration
First, calculate the ideal IRO correction voltage using the following formula, and select the nearest setting from Table 1: IROideal = - O(T1) x VBDRIVE (T1) = - (0.012V/V) x 2.5V = - 30mV where IROideal is the exact voltage required to perfectly null the sensor, O(T1) is the sensor offset voltage in V/V at +25C, and VBDRIVE(T1) is the nominal sensor excitation voltage at +25C. In this example, 30mV must be subtracted from the amplifier front end to null the sensor perfectly. From Table 1, select an IRO value of 3 to set the IRO DAC to 27mV, which is nearest the ideal value. To subtract this value, set the IRO sign bit to 0. The residual output-referred offset error will be corrected later with the offset DAC.
[
]
Determining OFFTC COEF Initial Value Generally, OFFTC COEF can initially be set to 0 since the offset TC error will be compensated in a later step. However, sensors with large offset TC errors may require an initial coarse offset TC adjustment to prevent the PGA from saturating during the compensation procedure as temperature is increased. An initial coarse offset TC adjustment is required for sensors with an offset TC greater than about 10% of the FSO. If an initial coarse offset TC adjustment is required, use the following equation:
OFFTC COEF = VBDRIVE (T) x 2.3 4096 x VOUT (T)
4096 x (OTC x FSO) x T 4096 x (-1000ppm/C x 4V ) -2100ppm/C x 2.5V x 2.3 TCS x VBDRIVE x 2.3 x T 1357
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17
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
where OTC is the sensor offset TC error as a ppm/C of OUTFSO (Table 8), T is the operating temperature range in C, and OFFTC COEF is the numerical decimal value to be loaded into the DAC. For positive values, set the OFFTC sign bit high; for negative values, set the OFFTC sign bit low. If the absolute value of the OFFTC COEF is larger than 4096, the sensor has a very large offset TC error, which the MAX1459 is unable to completely correct without the use of a temperature sensor. At this point, it is important that no other changes be made to the offset or offset TC DACs until the Offset TC compensation step has been completed. Step 2 To complete linear FSOTC compensation, take data measurements at a second temperature, T2. The following equation and procedure are suitable for any two arbitrary temperatures where T2 > T1. The following steps are performed at temperature T2: 1) Measure the full-span output (measuredVFSO(T2)). 2) Calculate VBIDEAL(T2) using the following equation: VBIDEAL (T2) = VBDRIVE x
FSO Calibration
Perform FSO calibration at room temperature with a fullscale sensor excitation: 1) Set FSOTC COEF to 1000. 2) At T1, adjust FSO DAC until VBDRIVE is about 2.5V. 3) Adjust offset DAC (and OFFSET sign bit, if needed) until the T1 offset voltage is 0.5V (see OFFSET Calibration section). 4) Measure the full-span output (measuredVFSO). 5) Calculate the ideal bridge voltage, V BIDEAL (T1), using the following equation: VBIDEAL (T1) = VBDRIVE x
desiredVFSO - measuredVFSO (T2) 1 + measuredVFSO (T2)
3) Set VBIDEAL(T2) by adjusting the FSO DAC. 4) Name the current FSO DAC coefficient D. 5) Change FSOTC DAC to 1000. 6) Adjust FSO DAC until VBDRIVE is equal to VBIDEAL(T2). 7) Name the FSO DAC coefficient C. Step 3 Insert the data previously obtained from steps 1 and 2 into the following equation to compute FSOTC COEF: FSOTC COEF = 1000 B - D + 3000 C - A +
desiredVFSO - measuredVFSO (T1) 1 + measuredVFSO (T1)

Note: If VBIDEAL(T1) is outside the allowable bridge voltage swing of (VSS + 1.3V) to (VDD - 1.3V), readjust the PGA gain setting. If V BIDEAL (T1) is too low, decrease the PGA gain setting by one step and return to step 2. If VBIDEAL(T1) is too high, increase the PGA gain setting by one step and return to step 2. 6) Set VBIDEAL(T1) by adjusting the FSO DAC. 7) Readjust Offset DAC until the V OUT = 0.5V (see OFFSET Calibration section).
() (B - D)
( (C - A)
)
Three-Step FSOTC Compensation
Step 1 Use the following procedure to determine FSOTC COEF; four variables, A-D, will be used: 1) Name the existing FSO DAC coefficient A. 2) Change FSOTC DAC to 3000. 3) Adjust FSO DAC until V BDRIVE (T1) is equal to VBIDEAL(T1). 4) Name the new FSO DAC coefficient B. 5) Readjust the offset voltage (by adjusting the Offset DAC), if required, to VOUT = 0.5V.
18
1) Load this FSOTC COEF value into the FSOTC DAC. 2) Adjust the FSO DAC until VBDRIVE(T2) is equal to VBIDEAL(T2). This completes both FSO calibration and FSO TC compensation.
Offset TC Compensation
The offset voltage at T1 was previously set to 0.5V; therefore, any variation from this voltage at T2 is an offset TC error. Perform the following steps: 1) Measure the offset voltage at T2. 2) Use the following equation to compute the correction required:
______________________________________________________________________________________
2-Wire, 4-20mA Smart Signal Conditioner
NewOFFTC COEF = CurrentOFFTC COEF 4096 VOFFSET (T1) - VOFFSET (T2) 2.3 VBDRIVE (T1) - VBDRIVE (T2)
[ [
]
]

Note: CurrentOFFTC COEF is the current value stored in the offset TC DAC. If the offset TC sign bit (SOTC) is low, this number is negative. 3) Load this value into the offset TC DAC. 4) If NewOFFTC COEF is negative, set the offset TC sign (SOTC) bit low; otherwise, set it high. Offset TC compensation is now complete.
mance and compensation requirements since they are used to measure many variables (e.g., pressure, acceleration, force, torque, etc.) and use a variety of materials for the sensing element (e.g., constantan, manganin, etc.) and spring elements (e.g., steel, glass, aluminum, etc.). This makes signal conditioning extremely application dependent. For more information on this application, refer to the MAX1459 Reference Manual.
MAX1459
Ratiometric Output Configuration
Ratiometric output configuration provides an output that is proportional to the power-supply voltage. When used with ratiometric A/D converters, this output provides digital pressure values independent of supply voltage. Most automotive and some industrial applications require ratiometric outputs. The MAX1459 provides a high-performance ratiometric output with a minimum number of external components (Figure 13). These external components include the following: * One power-supply bypass capacitor (C1) * Two optional resistors, one from FSOTC to ISRC, and another from ISRC to VSS, depending on the sensor type * One optional capacitor C2 from BDRIVE to VSS 2-Wire, 4-20mA Configuration In the 2-wire configuration, a 4mA current is used to power a transducer, and an incremental current of 0mA to 16mA proportional to the measured pressure is transmitted over the same pair of wires. Current output enables long-distance transmission without a loss of accuracy due to cable resistance. Only a few components (Figure 14) are required to build a 4-20mA output configuration. Use a low-quiescent-current voltage regulator with a built-in bandgap reference (such as the MAX875). Since the MAX1459 performs temperature and gain compensation of the circuit, the temperature coefficient and the calibration accuracy of the reference voltage are of secondary importance. The MAX1459 controls the voltage across resistor R SENSE. With R SENSE = 50, a 0.2V to 1.0V range would be required during the calibration procedure. Resistors RB, RC, and ROFF are used to set the voltage across RSENSE. For overvoltage protection, place a zener diode across V IN - and V IN + (Figure 14). A feedthrough capacitor across the inputs reduces EMI/RFI. For more information on this application, refer to the MAX1459 Reference Manual. In 4-20mA applications, pay close attention to thermal management. Q1 will dissipate significant power and, if
19
OFFSET Calibration
At this point, the sensor should still be at temperature T2. The final offset adjustment can be made at T2 or T1 by adjusting the offset DAC (and optionally the offset sign bit, SOFF) until the output (VOUT(PMIN)) reads 0.5V at zero input pressure. Use the following procedure: 1) Set offset DAC to zero (offset COEF = 0). 2) Measure the voltage at OUT. 3) If VOUT is greater than the desired offset voltage (0.5V in this example), set SOFF low; otherwise, set it high. 4) Increase offset COEF until VOUT equals the desired offset voltage. Offset calibration is now complete. Table 7 and Figure 12 compare an uncompensated input to a typical compensated transducer output.
Sensor Selection
Silicon Piezoresistive Sensors The MAX1459 is optimized for use with sensors designed for current mode operation that have a TCR in the neighborhood of 2000ppm/C or more. Voltagemode excitation sensors have a characteristically low TCR, which may necessitate the use of a temperature sensor (internal or external). For more information on using the MAX1459 in conditions such as TCR < TCS, low TCS, or low TCR, refer to the MAX1459 Reference Manual. The ideal sensor used with the MAX1459 will not change input impedance as a function of mechanical excitation (pressure). PRTs that are imbalanced behave poorly. Strain-Gauge Sensors The MAX1459 was optimized for signal conditioning of piezoresistive sensors; however, it offers powerful performance for signal conditioning strain-gauge sensors as well. Strain-gauge sensors vary greatly in perfor-
______________________________________________________________________________________
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
VIN+ 4-20mA 12V-40V
100 D Q2 PN4391 S G RX
VCC 5V
TransZorbTM 1F Ci IDD ~ 3mA AUXILIARY OP AMP (INTERNAL TO MAX1459) ROFF RB RY C Q1 B 2N2222 E
MAX875
GND 0.1F 1F
VDD
MAX1459
0.1F VSS CF RD
RC
GND
RSENSE
50
VIN-
Figure 14. 2-Wire, 4-20mA Circuit
placed close to the pressure sensor, can cause excessive errors. Of particular concern is an extremely long sensor-output settling time.
* Two power-supply lines * One analog output voltage line from the transducers to a system DVM * Two serial-interface lines: DIO (input/output) and SCLK (clock)
Nonlinearity Compensation
R TEMP can be used in conjunction with R ISRC and RFTC to compensate for sensor nonlinearity. For more information on this application, refer to the MAX1459 Reference Manual.
MAX1459 Evaluation _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Development Kit __________________
To expedite the development of MAX1459-based transducers and test systems, Maxim has produced the MAX1459 evaluation kit (EV kit). First-time users of the MAX1459 are strongly encouraged to use this kit. The MAX1459 EV kit is designed to facilitate manual programming of the MAX1459 and includes the following: 1) Evaluation Board with a silicon pressure sensor.
TransZorb is a trademark of General Semiconductor Industries, Inc.
Test System Configuration
The MAX1459 is designed to support an automated production pressure-temperature test system with integrated calibration and temperature compensation. Figure 15 shows the implementation concept for a lowcost test system capable of testing multiple transducer modules connected in parallel. Three-state outputs on the MAX1459 allow for parallel connection of transducers. A digital multiplexer controls the chip-select signal for each transducer. The test system shown in Figure 15 includes a dedicated test bus consisting of five wires:
20
______________________________________________________________________________________
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
DIGITAL MULTIPLEXER CS[1:N] CS1 CS2 CSN
MODULE 1
CS BDRIVE INP INM MAX1459
MODULE 2
CS BDRIVE INP INM MAX1459
MODULE N
CS BDRIVE INP INM MAX1459 SCLK OUT VSS VDD DIO OUT VSS TEST OVEN
SCLK DIO +5V VDD OUT VSS VDD
SCLK DIO
VOUT DVM SCLK DIO
Figure 15. Automated Test System Concept
2) MAX1459 Reference Manual, which describes in detail the architecture and functionality of the MAX1459. This manual was developed for test engineers familiar with data acquisition of sensor data and provides sensor compensation algorithms and test procedures. 3) MAX1459 Communication Software, which enables programming of the MAX1459 from a computer (IBM compatible), one module at a time. 4) Interface Adapter and Cable, which allow the connection of the evaluation board to a PC parallel port.
MAX1459 Pilot Production System
Maxim understands that one of the biggest challenges in pressure sensor design is the transition from prototype to production. To simplify this transition, Maxim has developed the fully automated pilot production system for volume applications. The system consists of the Maxim 14XXDASBOARD plus one or more 14XXMUXBOARD modules, a DVM, an environmental chamber, and a pressure controller.
Only the 14XXDASBOARD and the 14XXMUXBOARD modules are available through Maxim. The DVM, environmental chamber, and pressure controller must be acquired through other vendors. The 14XXDASBOARD, in conjunction with the 14XXMUXBOARD modules, allow compensation of up to 112 units. IEEE-488 commands select the active DUT and communicate with the MAX14XX application circuits. All system voltage measurements are multiplexed for use with a single external DVM. Each DUT interfaces to the 14XXMUXBOARD by means of a general-purpose transition board, which provides digital interface signals and low-noise analog inputs. The 14XXDASBOARD is required to operate the 14XXMUXBOARD. All driver software is incorporated into the 14XXDASBOARD firmware. Sensor compensation procedure is implemented using National Instruments' LabViewTM program.
LabView is a trademark of National Instruments.
______________________________________________________________________________________
21
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
You may have to adapt various portions of the compensation procedure if you are using a different pressure controller, oven, or DVM than what the system was designed to accommodate. Contact factory for pricing and availability.
Functional Diagram
VDD BDRIVE COARSE OFFSET (IRO DAC)
Customization
Maxim can customize the MAX1459 for high-volume applications. With a dedicated cell library consisting of more than 200 sensor-specific functional blocks, Maxim can quickly provide customized MAX1459 solutions. Please contact Maxim for further information.
INP INM
MAX1459
NBIAS PGA OUTPUT SELECT AMPAMP+ OUT
ISRC VDD AMPOUT
RFTC RISRC VSS 128-BIT EEPROM CONFIGURATION REGISTER 12-BIT D/A - OFFSET 12-BIT D/A - OFFSET TC 12-BIT D/A - FSO 12-BIT D/A - FSOTC RTEMP A=1
FSOTC
TEMP1
CS WE SCLK DIO
TEMP2
DIGITAL INTERFACE
TEMPIN
VSS
Chip Information
TRANSISTOR COUNT: 7792 SUBSTRATE CONNECTED TO VSS
22
______________________________________________________________________________________
2-Wire, 4-20mA Smart Signal Conditioner
Package Information
SSOP.EPS
MAX1459
______________________________________________________________________________________
23
2-Wire, 4-20mA Smart Signal Conditioner MAX1459
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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